High sensitivity latched comparator input and auto-synchronizing demultiplexer
Enables test and measurement, defense, and aerospace designers to develop high speed data acquisition front ends and to deserialize high speed signals
Features a high-speed sampling clock and high-bandwidth latched comparator input that can be used to sample high-bandwidth analog[] signals and demultiplex them to a lower data rate for post-processing via a low speed FPGA[] or ASIC
The high bandwidth input supports digital signals up to 12.5 Gbps, which are latched and deserialized to an eight bit parallel output bus
The 1:8 deserialization, coupled with an on-chip synchronization circuit and adjustable output levels, allow the use of multiple demultiplexers in parallel, with automatic alignment of the parallel output buses of the demultiplexers
Accepts a single external clock at up to 12.5 GHz that samples the input signal from the high-bandwidth comparator
Internally generated clocks are used for demultiplexing the latched input signal to an eight-bit parallel data bus
The device outputs a full-rate clock (1/8th of the input clock) or half-rate clock (1/16th of the input clock) as determined by the CLKSEL input
The DEMUX’s built-in synchronization circuit allows two or more units to be automatically synchronized using a master/slave mode, in which the slave DEMUX synchronizes to a signal (CK16) from the master, or a slave/slave mode, in which both units are synchronized to an external master clock (1/16 of the input clock frequency)
Synchronization occurs within at most 152 periods of the input clock
The 12.5 Gbps 1:8 Demultiplexer with Latched Comparator Input operates from a standard +3.3 V power supply
It is currently shipping in pre-production quantities in an 8 x 8 mm QFN package or on an evaluation board with SMA connectors, and full production is expected to begin in Q1 2008
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Part of the High Speed Logic family of devices
] signals and demultiplex them to a lower data rate for post-processing via a low speed FPGA[
