UltraSoC announces processor trace support for RISC-V
UltraSoC, headquartered in Cambridge, UK, provides SoC infrastructure for embedded systems based on advanced SoCs. It’s a natural extension for the company to move into the arena for the open-source RISC-V instruction-set architecture. The proponents for RISC-V are attempting to build up an ecosystem of tools, IP, software, etc., as quickly as possible. To that end, the company is offering processor trace support for products based on RISC-V. It has developed a specification for processor trace that will likely be adopted by the RISC-V Foundation as part of the open-source spec. UltraSoC intends to submit a proposed processor trace format to the RISC-V foundation later in 2017 as the basis of the open source standard implementation.
Five core vendors have already announced their support for the new trace specification: Andes, Codasip, Roa Logic, SiFive,and Syntacore. Processor trace functionality allows the behavior of a program to be viewed in detail, instruction-by-instruction, which is needed by software developers. Some claim that processor trace had been a significant missing piece in the RISC-V ecosystem from a debug standpoint.
UltraSoC’s implementation of RISC-V processor trace functionality will be available in the fourth quarter if this year.