Growing the pie: Eclipse-based Windows IDE gives more access to RISC-V developers
The RISC-V community received a significant boost last week, and while it has to do with Windows, it’s still based on open source.
Microsemi announced Thursday that the latest version of its free Eclipse-based integrated development environment (IDE),, now supports RISC-V development on Windows 7 and 10 operating systems (OSs). SoftConsole is the first Windows-hosted Eclipse IDE that supports the RISC-V instruction set architecture (ISA), and although Linux variants of the platform remain available, the latest release signals continued interest and expansion in the RISC-V ecosystem.
“When we started promoting our [RISC-V] core and gaining interest, people were asking for a Windows-based IDE,” says Ted Marena, Director of SoC/FPGA Product Marketing and Business Development at Microsemi and Vice Chair of the RISC-V Marketing Committee. “When we talk with an organization they may have a dozen software or firmware guys and 30 or 40 percent of them are Windows guys. Then there are companies that are standardized on Windows. Sometimes companies won’t move ahead without it.
“The SoftConsole IDE we released back in November was Linux-based, and many of the Linux IDEs out there weren’t that polished,” Marena continues. “What we introduced was an Eclipse-based IDE that people can depend on in the Linux-based version and now in the Windows version.”
SoftConsole 5.1 targets C/C++ development on all 32 and 64-bit RISC-V cores by integrating the, which includes support for the standard M (multiply/divide), A (atomic memory operations), F (single precision floating point), D (double precision floating point), Q (quad-precision floating point), G (general-purpose ISA), and C (16-bit compressed instruction set) extensions. The platform supports both Microsemi and non-Microsemi RISC-V targets, and has been validated thus far using the , , , and -based RISC-V soft CPUs, and .
[Figure 1 | In addition to now supporting development on Windows machines, the Microsemi SoftConsole 5.1 IDE enables embedded software and firmware engineers to design on all 32- and 64-bit RISC-V targets, from Microsemi or otherwise.]
The IDE is based on the GNU Compiler Collection (GCC), with hardware and software debugging provided through theusing dongles such as the and .
Riding open source RISC-V into commercial development
While RISC-V is firmly entrenched in the open source community it is also garnering commercial interest, particularly in industries such as aerospace, defense, security, and other safety-critical markets where the ability to inspect RISC-V RTL code provides additional assurances in terms of trust and functional safety. In these environments, engineers typically leverage RTL tools like Microsemi’s Libero IDE software for design entry, synthesis and simulation, place and route, timing, power and analysis, etc., as well as inspection.
This is not the purview of the embedded software and firmware developers, but is still extremely useful information to those engineers when writing firmware or application code. With the advent of SoftConsole 5.1, register files from the Libero IDE can now be output to the SoftConsole platforms to help optimize software based on target silicon (Figure 2). This integration will continue to be enhanced in the future, as Microsemi plans to link the Smart Debug features of Libero with a Smart Debug resource in SmartConsole that will tie processor logic stepping to firmware development. As a result, C/C++ developers will benefit from more and more visibility into transfer-level operations of the exact RISC-V cores they’re developing for.
Further integration of the SoftConsole platform will support OSs such as FreeTROS, SafeRTOS, LiteOS, and Micrium µC OSII/III, as well as the Microsemi Firmware Catalog. The Firmware Catalog, which is currently available as a standalone program, will be integrated directly into the SoftConsole platform to automate the process of downloading and installing RISC-V drivers for Microsemi RISC-V CPUs, as well as other processors and peripherals, through a hardware abstraction layer (HAL). Example code (or bitstreams) is also accessible in the Firmware Catalog (Figure 3).
Grab a piece of the [RISC-V] pie
Growth in development tools is usually a good indicator of the success of a processor architecture, which also appears to be the case with the RISC-V ISA. For their part, Microsemi encourages the RISC-V community to submit their hardware to be ported to the SoftConsole platform.
As Marena puts it, “this allows us to ramp the ecosystem for RISC-V cores more quickly.”
“The open source community wants people to be viewed as contributors, not suckers,” he adds.
For those interested in learning more, Microsemi will be presenting on SoftConsole and RISC-V at the www.microsemi.com/products/fpga-soc/design-resources/design-software/softconsole#downloads., and in July at . Free versions of the Linux or Windows SoftConsole 5.1 IDE can be downloaded today at