89PES12N3, 3-port, 24-lane PCIe Switch

12 PCI Express lanes (2.5 Gbps), 3 switch ports

February 21st, 2010

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  • Low latency cut-through switch architecture
  • 128 to 2,048 byte supported payload sizes
  • Fully compliant with PCI Express Base specification Revision 1.0a
  • One port configurable as downstream port or nontransparent
  • Automatic per port link width negotiation to x4, x2, or x1
  • Ability to load device configuration from serial EEPROM
  • Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement en-to-end CRC (ECRC)
  • Supports ECRC in transparent and non-transparent modes
  • Supports PCI Express native hot plug, hot swap
  • Utilizes advanced low power design techniques to achieve low typical power consumption

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