Clock gating is a well understood power optimization technique employed in both ASIC and FPGA designs to eliminate unnecessary switching activity. This method usually requires the designers to add a small amount of logic to their RTL code to disable or deselect unnecessarily active sequential elements — registers, for example. Despite the obvious value of reduced dynamic power afforded by this method, the designer faces significant challenges when attempting to perform these optimizations manually.



Xilinx intelligent clock-gating optimizations are automatically performed on the entire design, introduce no new tools or steps to the flow (compared to thedefault flow), and generate no changes to the existing logic or clocks that would alterthe behavior or timing of the original design version.