PCI Express over M-PHY: Proven technologies scale I/O performance to meet mobile needs - Q&A with Rick Wietfeldt, MIPI Alliance and Al Yanes, PCI-SIG
The MIPI Alliance and PCI-SIG recently announced an agreement to deliver an adaptation of the PCI Express (PCIe) architecture over the MIPI M-PHY physical layer technology to provide scalable I/O functionality for mobile devices. Rick and Al describe how this collaboration combines the interoperability of the PCIe standard with the power efficiency of the M-PHY physical layer to create a low-power, high-performance technology for the mobile market.
ECD: What is the MIPI Alliance, and how does it help embedded device developers?
WIETFELDT: MIPI Alliance is an organization with global membership focused on developing interface standards for mobile devices. These interface standards include high-speed gigabit-per-second interfaces for performance applications such as wireless modems, cameras, and displays, as well as low-speed and multipoint interfaces for other applications such as audio and control. Key MIPI objectives include achieving low-power operation for battery-constrained mobile devices and minimizing the diversity of interfaces that speed OEM time to market. Embedded device developers benefit from a well-known and optimized set of industry-standard interfaces.
ECD: What is the PCI-SIG, and how does it help embedded device developers?
YANES: The PCI-SIG is the industry organization chartered to develop and manage the PCI Express (PCIe) standard. With a global membership community, the PCI-SIG’s principal charter is to evolve the PCIe architecture to meet the current and emerging needs of its members and the industry. A board of directors comprising nine people, each elected by the membership, leads the PCI-SIG. The PCI-SIG fulfills its charter by continuing to promote innovation and evolving through interoperability testing, technical support, seminars, and industry events.
As PCs become lighter and thinner and tablets and smartphones become more functional, consumers want seamless, always on/always connected functionality from their computing devices. To respond to these market expectations, device manufacturers need efficient, intelligent I/O technologies. The PCIe architecture satisfies all of these requirements, and with the adaptation to operate over the M-PHY specification, it can deliver consistent high performance in power-constrained platforms such as Ultrabooks, tablets, and smartphones. By delivering this technology, the PCI-SIG is meeting the emerging needs of its members and the industry.
ECD: What is M-PHY physical layer technology, where is it currently deployed, and what can we expect in the near future?
WIETFELDT: The M-PHY physical layer was developed to satisfy the anticipated needs of mobile devices including high performance, low power, and high Electromagnetic Interference (EMI) immunity. High performance is achieved through three “gears” of operation including Gear 1 at 1.45 Gbps/lane, Gear 2 at 2.9 Gbps/lane, and Gear 3 at 5.8 Gbps/lane. Each gear includes two closely spaced frequencies of operation providing the capability to select operating frequency based on optimal mitigation of EMI issues in the mobile device, such as ensuring adequate radio receive sensitivity.
M-PHY provides key bandwidth scalability via support for varying lane widths – typically one, two, four, or eight lanes – and bandwidth asymmetry via differing numbers of lanes in the transmitter/receiver directions. M-PHY was also designed to accommodate a variety of overlay protocols for different applications, such as USB 3.0 or PCIe for chip-to-chip connections, Camera Serial Interface to camera sensors, and Display Serial Interface to (internal) displays. The flexible support for differing protocols provides a key foundational element for broad use of MIPI M-PHY technology in a number of different applications within a mobile device.
M-PHY has been broadly accepted within key industry organizations developing interfaces for specialized applications. JEDEC has adopted M-PHY for its Universal Flash Storage (UFS) interface as an evolution to the embedded Multi-Media Card (eMMC) interface for embedded storage. USB-IF has selected M-PHY for its SuperSpeed Inter-Chip (SSIC) interface for transporting the USB 3.0 protocol. And most recently, the PCI-SIG has chosen M-PHY for use as a low-power PHY to carry the PCIe protocol.
ECD: What was the impetus behind this collaboration to develop an adaptation of PCIe over M-PHY, and how will this technology be implemented in mobile applications?
YANES: PCI-SIG is interested in adapting its ubiquitous PCIe architecture to operate on the MIPI M-PHY to provide a robust I/O architecture for use by its members interested in ultra-low-power solutions. MIPI has succeeded in defining a best-in-class low-power, scalable PHY (M-PHY). The layered architecture of PCIe allows for an easy way to replace the physical layer with a new PHY. This design uses the M-PHY layer combined with the PCIe data link and transaction layer.
WIETFELDT: The collaboration to develop the PCIe on M-PHY solution stemmed from the need in increasingly powerful mobile computing devices to merge the ubiquitous PCIe protocol on the emerging M-PHY physical layer. Similar to the joint MIPI/USB-IF development of the SSIC specification, known informally as “USB 3.0 over M-PHY”, the joint MIPI/PCI-SIG development of the “PCIe over M-PHY” technology (see Figure 1) delivers high performance and broad ecosystem support of applications in the PCIe market, as does SSIC in the USB market and application space.
ECD: How can PCIe technology reduce product development schedules and cost?
YANES: As a broadly adopted technology standard, PCIe benefits from several decades of innovations with universal support in all major operating systems, a robust device discovery and configuration mechanism, and comprehensive power management capabilities that few, if any, other I/O technologies can match. PCIe technology has a flexible, layered protocol that enables innovations to occur at each layer of the architecture independent of the other layers.
PCIe architecture meets the software support and testability needed for today’s power-constrained platforms; no new development or investment in the architecture is needed. In this way, power-efficient PHY technologies such as MIPI M-PHY can be integrated with the familiar and highly functional PCIe protocol stack to deliver best-in-class and highly scalable I/O performance in mobile devices such as Ultrabook, tablet, and smartphone devices.
ECD: Can this new technology be used in traditional embedded applications other than mobile?
YANES: PCIe is currently deployed in a number of embedded platforms that run the gamut from enterprise to consumer applications and form factors. With the adaptation to support the M-PHY, this ubiquitous I/O technology has been rendered suitable for adoption in Ultrabook, tablet, and smartphone platforms almost overnight. In addition, it is expected that this technology will be adopted in future storage applications in various topologies due to the anticipated migration of storage attach points from SATA to PCIe technology. As a power-efficient, general-purpose, load-store I/O architecture, component and device designers can implement this technology in other I/O expansion usage models of their choice.
WIETFELDT: While the MIPI Alliance develops interface standards primarily for mobile devices such as smartphones, tablets, and other consumer electronics, MIPI interfaces can be used in products not employing wireless communications. The primary difference is nontechnical and relates to MIPI’s licensing model, which involves Reasonable and Non-Discriminatory – Zero Cost (RANDZ) terms for mobile devices and Reasonable and Non-Discriminatory (RAND) terms for other devices. This licensing model is very common in the high technology industry.
ECD: Does the MIPI Alliance or PCI-SIG offer any software tools, libraries, and educational materials to help embedded designers get started with these standards?
YANES: PCI-SIG offers a range of technical support for members, including test specifications and procedures, compliance workshops around the world, and annual developer conferences to help members design and implement PCIe standards.
WIETFELDT: MIPI Alliance offers an , which includes general interface tutorials, specification tutorials, white papers, webinars, and other presentations/videos. MIPI Alliance also provides a suite of testing resources, which includes test suite documents, test tools, and multivendor interoperability events.
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