Verification is crucial for programmable SoC designs
A classic signal processing approach is decimation, using hardware techniques to preprocess high-speed incoming data into a more manageable lower-rate stream for software to operate on using one or more compute cores. Decimation suits applications such as embedded vision, software-defined radio, radar and lidar, and newer ideas including multiprotocol IoT gateways and real-time data analytics platforms.
Modern FPGAs are ideal for creating the required hardware processing. With high-speed transceivers and other I/O, logic blocks including multiply-accumulate functions, on-chip memory, and fast interconnect fabrics, FPGA-based designs can be revised as necessary until their functional performance is proven.
Software processing fits on a general-purpose microprocessor core. An advantage of using software is exploration; algorithms can be tested, tuned, and changed out with just a recompile. I/O blocks such as Ethernet, HDMI, PCIe, USB, and others are easily supported with various protocol stacks. Presentation and visualization of processed data are also handled on the software side.
Hybrid chip, separate disciplines
Many signal-processing system designs combine FPGAs with microprocessors using separate parts. The benefits of a hybrid architecture inspired creation of the all-programmable system-on-chip (SoC), such as the Xilinx Zynq-7000 family. Integrating programmable logic and I/O with a pair of ARM Cortex-A9 processing cores on one chip provides a path for execution of many hybrid system designs, scalable by choosing the appropriate Zynq part.
Zynq has gained immense popularity among system designers. Wide availability of FPGA intellectual property (IP) blocks, many in Xilinx-curated libraries, combined with the Xilinx Vivado Design Suite for tackling custom designs, makes the process of hardware creation much easier. This is especially true for those already familiar with FPGA design techniques. Xilinx also offers PetaLinux tools for working with open-source software such as Linux and the Yocto build system.
Several merchant board vendors offer Zynq-based products, some with low-end Zynq parts targeting makers, some with higher end parts delivering more performance. Features on these boards vary, but most present the Zynq on-chip I/O complement and offer some expandability with daughterboard interfaces.
So, what’s missing? Zynq unified the hardware and software design in a single part, but still requires two unique development disciplines. On the microprocessor side, Zynq software development looks very familiar. For most hardware customization efforts using the programmable logic side, designers still need to be proficient in a hardware definition language such as RTL, VHDL, or Verilog. Vivado tools are capable in FPGA synthesis and debug, with some recently added basic simulation capability.
Decimation approaches typically handle critical data at high speeds. Rather than just a collection of random logic, decimation requires careful orchestration of functions with deterministic timing. An experienced FPGA designer can implement a design, test it, iterate as necessary, and converge to what looks like a working configuration given sufficient test coverage. This is one advantage of FPGA-based prototyping strategies; a design can be co-optimized, in hardware and software, before committing to a product.
High-performance verification is crucial
Danger arises around conditions in an FPGA design that may not have been thoroughly explored with the right tools. The burden of proof for an FPGA design dealing with critical data is really no different than that for a purpose-built SoC, despite the fact that programmable logic can be modified quickly during development with almost no expense compared to redesigning a chip. Once fielded, a flaw in an FPGA design is the same as any other hardware design flaw.
No prudent SoC designer would skip a robust verification testbench; with SoC designs costing millions to execute, failure in silicon is much more expensive than testing. Yet FPGA designers sometimes minimize this vital step because of the effort needed to gather, configure, and become proficient with more advanced simulation and debug tools.
For Zynq designs, there’s a verification option beyond the basics found in Vivado, one allowing designers to keep the efficiency of Vivado synthesis yet gain significant capability at simulation and debug. Aldec Riviera-PRO, an advanced verification platform, integrates directly as a TcL application in Vivado and is part of Xilinx’s release testing, providing high-performance simulation and debug.
With a massive increase in simulation performance and support for more language constructs, testbenches are more powerful and can execute more test cases. Extended debugging supports tracing, waveform, dataflow, finite state machine (FSM), and array plotting capabilities. The result is better coverage and more complete verification of the Zynq programmable logic, achieved in less time without complex tool integration efforts.
Embedded kits for Zynq design
Going a step further, Aldec is venturing into embedded design for the first time with the TySOM Embedded Development Kit. The kit is a fully configured environment for Zynq development, addressing the needs of both hardware and software development teams while enabling robust verification needed for confidence in handling critical data.
TySOM-1 is based on the XC7Z030 with I/O including HDMI, audio, GigE, PCIe, USB 3.0, and a Digilent Pmod-compatible header for expansion. TySOM-2 is based on the higher performance XC7Z035, XC7Z045, or XC7Z100 with I/O including HDMI, GigE, USB 2.0, and two FMC HPC connectors for expansion. Both boards also feature analog-to-digital converters, temperature sensors, and accelerometers.