VPX helps programmable field of dreams become reality

4Thanks to the mind-boggling processing power available in the newest FPGAs and the organizational structure of 3U OpenVPX systems, a new generation of miniature ruggedized hardware designs is possible. Commercially available hardware combining these technologies allows engineers to quickly and easily build compact systems for the most demanding tasks.

Thirty-six multigigabit transceivers, 850 high-speed General-Purpose I/O (GPIO), and 2 million reprogrammable logic cells seem like a digital designer’s dream come true. So why does architecting systems with the industry’s newest FPGAs sometimes feel like a nightmare? Somewhere between trying to line up 10 Gbps transceiver lanes, Complementary Metal Oxide Semiconductor (CMOS) control signals, and Low-Voltage Differential Signaling (LVDS) sensor interfaces, designers may swear they’ve seen Freddy Krueger sneaking around.

Fortunately, finding a compact, open architecture that doesn’t decimate an FPGA’s outstanding I/O capability is easy to accomplish using 3U VPX cards, which offer an ultrarugged form factor loaded with I/O that can operate at 10 Gbps. Most importantly, the VPX universe utilizes a standardized control and data flow architecture supported by vendors around the world, letting designers utilize every square inch of the latest, most massive FPGAs on the market.

OpenVPX opens design possibilities

Having an interconnect scheme with a high pin count and outstanding signal integrity sounds powerful, but it isn’t useful without an organized and widely accepted architecture behind it. The OpenVPX architecture has moved VPX from a highly customized embedded system into the realm of COTS rugged computing. The most common OpenVPX architecture is similar to modern PCI Express (PCIe) desktops, with a central processing/control card operating a PCIe switch (see Figure 1). A standard backplane carries the PCIe end points to an arbitrary number of peripheral cards, just like the motherboard in a desktop computer. The biggest difference is that VPX can withstand vibration, shock, and temperature extremes that would send a desktop PC to an early grave.

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Figure 1: In a five-slot OpenVPX system with a PCIe architecture, a standard backplane carries PCIe end points to the peripheral cards.
(Click graphic to zoom)

Beyond benefits provided by a fast data backplane, OpenVPX offers options for control over Ethernet and ultrafast SATA solid-state drives. Processor cards work best as system controllers, thanks to their built-in PCIe arbitration functionality. However, FPGAs have a distinct advantage for peripheral cards. They give OEMs the ability to use almost every standard configuration option available with a single piece of hardware, which translates directly into design flexibility for system integrators.

Massive I/O brings reconfigurable options

With organized data and control lines, a few rays of light are starting to filter through the initial design nightmare. Add the flexibility and speed of an FPGA, and the scare factor is reduced even further. However, a system can’t be composed of just a few SATA devices, PCIe lanes, and an Ethernet connection alone.

Enter the knight in shining armor, reconfigurable I/O. This technology has been one of the biggest advantages in FPGAs since their conception, and it is making strides again with VPX. A single 3U VPX card slot has three interface connectors on the backplane: P0 is for power and system management; P1 is for the OpenVPX architecture; and P2 is entirely reserved for user-defined I/O. That’s a whopping 72 pins with a max speed above 10 Gbps.

VPX also defines a handful of standard I/O arrangements to help designers correctly line up multigigabit lanes and lower-speed GPIO. The FPGA goes a step further, allowing the multigigabit lanes to operate over a wide range of speeds and signaling standards such as XAUI, 1000BASE-X, Serial RapidIO, and many more. On the low-speed side, pin flexibility ranges from 3.3 V CMOS down to LVDS in a single COTS hardware design.

The VPX P2 connector offers several options, but designers can find even more configurability on the module’s front-panel side. Due to wide industry adoption, modular front-panel I/O is common and supported by multiple vendors. FPGA Mezzanine Cards (FMCs) offer the widest range of industry support and deliver 160 GPIO and 10 multigigabit SERDES links that can run at 10 Gbps each. The market is filling up with front I/O modules that enable system architects to perform practically any task desired, including high-performance analog capture, video processing with Camera Link, copper and optical SERDES, 10BASE-T, RS-232/422 control, and simple GPIO. Where there are gaps in industry-wide offerings, various OEMs are delivering custom, low-cost products with short lead times (see Figure 2).

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Figure 2: Products such as the OpenCOTS 3U Conduction-Cooled VPX Development Kit offer designers support for developing 3U VPX modules with front I/O and an FMC site. Image courtesy of WaveTherm (www.wavetherm.com).
(Click graphic to zoom)

Ready for rugged deployment

To leverage these unlimited connectivity options, massive FPGA processing power, and an architecture that is practically plug-and-play, designers need the ability to package it all up and put it into an environment where only cockroaches could survive. VPX is designed to handle every environment imaginable. Simple forced-air lab and commercial deployment chassis are low cost and readily available. This is particularly useful when prototyping designs using rear I/O modules before integrating up to fully rugged deployment versions.

To help transition from the lab to deployment in a scorching dust-filled desert or at 40,000 feet, OEMs offer conduction-cooled versions of their hardware to get the heat out without airflow. The 3U form factor also helps reduce the length of metalwork between the ambient environment and the blazing-hot components in the middle of the board. For applications trying to defy the laws of thermodynamics, liquid flow-through chassis can actively suck the heat out of boards with incredible efficiency and without any degradation at altitude or fear of dust contamination.

VPX and FPGA technology in action

Add all of these elements together, and system integrators will find they can create compact, cost-effective, ultrarugged systems for a plethora of challenging applications. Understanding the power of VPX takes a run through the ropes. The hardware can fulfill any designer’s dream by providing the following capabilities, as illustrated in the application in Figure 3:

  • Output: A live video feed overlaid with directional vector graphics pointing out targeted radar signal sources
  • Inputs: Full Camera Link feed of high-altitude video, GPS, and RF input tuned to suspect radio frequencies

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Figure 3: OpenVPX hardware equipped with the latest FPGAs can provide the I/O functionality needed in a DF-Camera overlay system.
(Click graphic to zoom)

This is not a simple task, but the hardware to accomplish this is already built and ready to order. The user interface could be a workstation or flight control unit with a 10 GbE link to view the live video stream.

A processor card utilizing a Zynq processor with integrated programmable logic could easily manage the system control. Mount this on a PCIe switch card, and the processor XMC gains four lanes of PCIe Gen2 access to each VPX slot. The second slot has Camera Link front I/O passing 5.4 Gbps of raw camera data to an FPGA for preprocessing. In the third slot, a VPX carrier with an FPGA XMC card and a dual ADC front I/O card takes in the DF radar signals and processes them into directional information regarding the radar source. Lastly, a GPS receiver decodes the information from a GPS antenna to deliver a high-resolution high-refresh rate for location, altitude, and velocity data to help align the RF and image data. OpenVPX even has a standardized 1 PPS distribution system built into the backplane to keep all boards in sync with current GPS information.

This is all completed using Xilinx’s latest Virtex-7 FPGAs, which offer greatly reduced power consumption compared to previous generations. By using reconfigurable logic at every stage in the design, the entire internal communication architecture can be configured to achieve the highest possible performance. For example, data can be passed between slot 2 and slot 3 with a 10G or 40G SERDES link over the OpenVPX expansion plane using the four-lane PCIe link or user I/O on P2. Virtex-7 FPGAs also come with the Vivado Design Suite, which was written from the ground up to allow teams of engineers to work collaboratively on complex projects like this.

Another impressive feature of this hardware is a highly upgradable and expandable framework. Say a designer wants to add another feature that requires a whole new input device and some heavy processing power. This system supports an additional PCIe link to slot 5 allowing future expandability without a system redesign. The hardware itself is upgradable, as Alpha Data and other OEMs continue to release boards with the newest FPGAs year after year.

Take the design another step further and add a few terabytes of solid-state storage for video recall. Use the mSATA slots located under the XMCs, or populate the empty VPX slot with one of many 3U VPX storage drives available from various manufacturers. All of this hardware is currently available on the market today. No need to wait for hardware design cycles and board reruns; just submit a purchase order and find some good programmers.

Sleeping easy

It’s time to say goodbye to those design sessions with your favorite horror movie character because the nightmare is finally over. The combination of 3U OpenVPX systems and the unreal processing power of modern FPGAs is creating a new generation of miniature, ruggedized hardware designs. Take advantage of these technologies and see how good it feels to start sleeping easy.

Kevin Roth is an Electrical Engineer at Alpha Data.

Alpha Data kevin.roth@alpha-data.com www.alpha-data.com

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