Aldec Announces HES-7, the Largest Off-The-Shelf Xilinx Virtex-7 FPGA Prototyping System at up to 288 Million ASIC Gates Capacity
Aldec unveils the largest in the industry, off-the-shelf Xilinx(r) Virtex(r)-7 prototyping system for SoC and ASIC designs, offering up to 288 million ASIC gates capacity.
Aldec Delivers Unprecedented Scalability and Verification Acceleration with the Latest Release of HES-DVM
Aldec, Inc. delivers new functionality to existing hardware resources and enables unprecedented scalability with the latest release of its hardware emulation solution software, HES-DVM 2014.12.
Aldec announces the latest release of its requirements lifecycle management solution for FPGAs/SoCs, Spec-TRACER(tm) 2014.12.This release delivers direct integration with IBM Rational DOORS, allowing board requirements and attributes in DOORS to be imported directly into the Spec-TRACER database.
Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM
OS-VVM delivers advanced verification test methodologies, including Constrained and Coverage-driven Randomization, as well as Functional Coverage, and provides advanced features to engineers designing ASICS and FPGA-based applications using VHDL.
Aldec adds Mirror-Box(tm) debugging technology to hardware-assisted simulation platform Mirror-Box(tm) to be formally announced and demonstrated in Booth #204 at EDSFair in Japan
Aldec Inc., a pioneer in mixed HDL language simulation and hardware-based assisted verification solutions for FPGA and ASIC designs, announces the release of a new debugging technology called Mirror-Box(tm) to the HES(tm) platform.
Aldec, Inc., unveils a new $1,995 mixed language RTL simulator -- Active-HDL(tm) Designer Edition. The product includes: industry proven IEEE mixed-language simulation support for VHDL, Verilog(r) and SystemVerilog (Design), 2X-plus performance gains over FPGA vendor supplied RTL simulators, encrypted IP support and no performance limitations on FPGA design size.
Renesas installs Aldec's New Server Farm Manager (SFMTM); Aldec's Regression Automation enables Renesas to manage 10,000 HDL Simulators concurrently
Renesas plans to utilize Aldec's new Server Farm Manager (SFM) to automate the process of running over 100,000 test vectors on Linux 64-bit machines. Using SFM will provide RVC with parallel verification of its microprocessor based system-level designs.