 | | Toshiba Expands Use of Altera Devices to Meet the High-Performance, Low-Cost Requirements of its Latest Flash Memory Video Solution |
| Company demonstrates lowest power midrange FPGAs with 10.3125-Gbps transceivers optimized for wireless, broadcast, and military applications |
| Provides users with single-chip solutions that integrate an industrial-grade dual-core 800 MHz ARM Cortex-A9 processor with Alteraís 28 nm low-power Cyclone V and Arria V FPGAs |
| Stratix V FPGAs are built to meet the requirements of next-generation 100-GbE system designs. Stratix V GX FPGAs deliver optimal bandwidth by providing integrated 14.1-Gbps transceivers with hardened 100G PCS functions on a 28-nm high-performance (28HP) process technology. |
| Stratix V FPGAs are built to meet the requirements of next-generation 100-GbE system designs. Stratix V GX FPGAs deliver optimal bandwidth by providing integrated 14.1-Gbps transceivers with hardened 100G PCS functions on a 28-nm high-performance (28HP) process technology. |
| Internal clock frequency rates up to 500 MHz and typical performance >250 MHz |
| The HD WDR video surveillance chipset comprises an Altera Cyclone IV E FPGA loaded with image processing IP bolted to an image sensor, and it provides High Def Wide Dynamic Range plus logic security |
| Industry’s First FPGA-based Soft Processor Supported by Wind River’s VxWorks RTOS |
| Altera's EFEC7 and EFEC20 are ultra high gain, hard decision FEC cores that enhance 100G networks and provide the smallest FPGA-based EFEC implementation available in the industry today |
| Provide a new partial reconfiguration method |
| Up to 50 percent lower total power compared to other equivalent density CPLDs on the market |
| With the variable-precision DSP block, Altera’s Stratix V FPGA can support – on a block-by-block basis – various precisions ranging from 9-bit x 9-bit up to single-precision floating point (mantissa
multiplication) within a single DSP block |
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