ELSTREE, England and MOUNTAIN VIEW, California, July 19, 2006 – ARC International plc. (LSE: ARK) and Azuro, Inc. today announced that Azuro’s PowerCentric low power methodology now is available for ARC™ licensees designing audio- or video-centric digital chips for embedded applications. With the use of Azuro’s PowerCentric in existing Cadence, Synopsys or Synplicity design flows, customers of the configurable ARC Media Subsystems and CPU/DSP[
] processors can reduce power consumption of the ARC-Based™ logic by more than twenty percent. This complements the existing ability of ARC licensees to achieve the industry’s lowest power consumption of any 32-bit configurable processor or subsystem through the use of ARC’s patented ARChitect configuration tool, where unneeded elements can be eliminated to dramatically reduce power usage.
Results were achieved after layout and timing closure using the Azuro PowerCentric solution on an ARC™ Video subsystem core in a 130nm process. Results were compared against an industry standard EDA[] flow which included clock gating and clock tree insertion.
“ARC continuously strives to offer best-in-class configurable solutions that fit the stringent needs of customers designing SoCs for power sensitive applications,” said Peter Hutton, senior vice president of engineering at ARC International. “By leveraging Azuro’s PowerCentric low power methodology, licensees can further reduce power consumption of ARC’s configurable subsystems and processors by more than 20% without impacting processor footprint.”
Azuro’s PowerCentric uniquely combines clock gating and clock buffering into one unified low power clock implementation solution which completely replaces clock tree synthesis in existing industry design flows. A demonstration of the technology on an ARC™ Video Subsystem will be available to qualified companies at the 2006 Design Automation Conference (DAC) in San Francisco. Interested parties should contact Azuro for more information.
Ashutosh Mauskar, vice president of product marketing for Azuro, said, “By incorporating Azuro’s PowerCentric into design flows for ARC’s products, our mutual customers are able to deploy extremely power efficient silicon. We are happy to be a low power solution for ARC licensees and look forward to future collaborations with the leader in configurability.”
Availability
Azuro’s PowerCentric solution for ARC’s configurable subsystems and processor families is available now from Azuro, Inc.
About ARC International plc
ARC International is the world leader in configurable subsystems and CPU/DSP processors that are used by semiconductor companies worldwide for next-generation system-on-chip (SoC) design. ARC’s patented configurable processor technology enables the development of consumer, networking, mass storage and other cost-sensitive devices that are smaller and provide a higher degree of differentiation over what can be created using “fixed architecture” core alternatives.
ARC International maintains a worldwide presence with corporate and research and development offices in California and Elstree, UK. For more information visit www.ARC.com. ARC International is listed on the London Stock Exchange as ARC International plc (LSE: ARK).
About Azuro
Azuro, Inc. is a provider of innovative electronic design automation (EDA) solutions that significantly reduce the power consumption of digital semiconductor chips. Founded in 2002, the privately held company is headquartered in Mountain View, Calif., with a development center in Cambridge, UK. For further information, visit www.azuro.com or call (650) 237-3500.
