June 7, 2010, Santa Clara, CA — Blue Pearl Software announces False Path Audit Trail, or FPAT(TM), a major new feature within Blue Pearl Software’s Cobalt(TM) Timing Constraint Generation Tool. FPAT automatically identifies the logical conflicts that prevent path activation and produces a constraint origination report and schematic view.

FPAT provides added reassurance of the validity of automatically generated constraints by giving designers a simple way to understand the reasons why paths in their design are false.

“We are committed to helping semiconductor designers obtain the highest level of confidence in their design with powerful new features in our tools,” said Ellis Smith, CEO of Blue Pearl Software.

Cobalt Timing Constraint Generation automatically analyzes RTL and generates false and multi-cycle path timing constraints. It outputs an SDC file containing timing exceptions along with an assertion file that can be used to verify the constraints using simulation or formal property checking.

Blue Pearl Software also offers Azure(TM) Timing Constraint Validation, which includes a built-in state-space search technology based formal property checker that can validate generated or legacy timing constraints.

Together, these three built-in verification capabilities give designers the highest level of confidence when utilizing timing exception constraints, providing substantial reductions in design risk.

About Blue Pearl Software

Headquartered in Santa Clara, Calif., Blue Pearl Software is privately-held electronic design automation (EDA[]) company committed to reducing iterations in digital design flows and improving design productivity.

For the latest news and information on Blue Pearl Software and for evaluation of Indigo RTL Analysis, Cobalt Timing Constraint Generation and Azure Timing Constraint Validation software, visit www.bluepearlsoftware.com.