Here’s a quick sampling of some of the pre show news that reached me for Embedded Systems Conference Silicon Valley 2010, and some comments with insights from the insiders and my thoughts you won’t see in the press releases. What we’re seeing: low power processors with 1GHz cores, big FPGAs and interesting usages like ultrasound, and …

Marvell announced their ARMADA 310 processor. ARM-derived core at 1GHz, less than 1W. The coolest part of their architecture is the crossbar – it’s the same crossbar from their Discovery series, capable of routing just about anything to anything inside the device. They’ve also gone DDR3 for the memory – according to Bob Salem, director of product marketing, they think the price crossover from DDR2 to DDR3 is this year. That’s the first time I’ve heard someone say that out loud.

Speaking of memory, Virage Logic announced they’ve moved their SiWare into 28nm, allowing creation of SoC onchip memory in advanced processes. There were some feature improvements, such as support for up to 16Mbit, but according to Lisa Minwell, director of tech marketing, the real story here is maturity and risk. These tools and techniques have been completely proven out at 40nm, and are now ready to move into cutting edge designs at 28nm.

Nice segue to 28nm, because Altera’s new Stratix V is there. With up to 1.1 million logic elements (LEs), 53-Mbits embedded memory, 3,680 18×18 multipliers and integrated transceivers operating up to an industry-leading 28 Gbps, it’s the latest in big and fast FPGAs and is after some very large apps. Also featured are improved partial reconfiguration capability and Embedded HardCopy blocks, which provide the equivalent of 700K additional LEs with 65 percent lower power compared to a soft logic implementation. It’s interesting that they want the ASIC and ASSP market with this device, and maybe the size/volume/price equation has finally swung in favor of FPGAs – we’ll see, but it’s clear there are applications where bigger FPGAs with faster communication capability will fit right away.

AppliedMicro weighed in on the AM82181 processor. They’re after a specific niche with this SoC – consumer storage and media server devices. Gopi Sirineni, Vice President of SMB and Consumer Business, said a couple big things in this design are the line-rate floating point that is needed for 11n Wi-Fi and NAS apps. They have a crossbar, too, capable of 5Gbps, and the RAID 5 is implemented in hardware. I asked them where they are going to get their RF, and they said watch for news with Atheros.

Samplify brought in something quite interesting, a 32-channel analog[] front end on a SO-DIMM module. “It’s a laptop-friendly form factor,” said Allen Evans, VP of marketing. And today we see why – they’ve also introduced a partnership with Altera where the AFE does the “heavy lifting” in a low-power Cyclone IV-based reference design for handheld ultrasound systems. “With the fragmentation in the ultrasound equipment industry, and the move to 65nm and volumes, it’s impossible to justify an ASIC in this application,” said Evans. Two people saying that this week. This whole idea of how better analog technology improves digital signal processing warms my heart as an analog guy, but where this could go is even more heartwarming. Evans also is pointing to something very cool – maybe, in the near future, this will be small and low-power enough to put in a mobile device with an expansion slot and an app. Hmmmmm.

Finally, LSI and their new APP3100 multicore communication processor creates a “bump-in-the-wire” needing only a 23×23 SoC and a power supply, no external memory required. Jim Sepko, Multicore[] Communication Processor product manager, said this is for wire-speed security at 1Gbps and takes less than 3W. While they’re after some bigger apps like base stations needing MEF-compliant traffic management, the 3W point also makes this appropriate for smaller appliances and devices. They also announced the Terari T2500 content processor, which can not only process security but also spot traffic type (for instance, video) and respond properly for the application to keep the user experience good. It’s a big multicore engine with and can work both ways, either having more packets spread across cores or having up to 12 threads working on a single packet, according to John Bromhead, Tarari Content and Security Processor Marketing. 100Gbps application recognition is an interesting use for DPI and a network processor.

All for now, thanks to all the folks who briefed me and looking forward to what else develops here in the next couple days.