SoC and ASIC designers got a major boost this week with news of the HAPS-60, the latest high-speed ASIC prototyping platform from Synopsys. A major upgrade over the previous generation, the HAPS-60 takes on designs with up to 18M ASIC gates with a single board, and multiple boards can be connected for even larger designs.
The first comment George Zafiropoulos, VP of solutions marketing for Synopsys, made was that “SoC and ASIC designers don’t have time to do [a system like the HAPS-60].” That sounds self-serving until one looks at what went into the HAPS-60. The design doesn’t simply plop 4 Xilinx Virtex-6 devices on the HAPS-64 board. It’s a 40 layer board supporting operation up to 200 MHz, with uniquely engineered material and traces to ensure signal integrity. The design also includes a high speed TDM interconnect between FPGAs, providing up to 7000 signals via 1Gbps muxed links.
Larry Vivolo, director of solutions marketing, shed some light on the DesignWare line of Synopsys IP – much of it has been built and verified on HAPS platforms. For instance, the USB 3.0 prototype for DisplayLink shown at CES 2010 was built on one of these systems. That’s an interesting statement in and of itself – customers looking to develop with cutting edge IP need to look to someone with experience in developing and verifying cutting edge IP.
Making the system do valuable work is also central to the design. The HAPS-60 includes a Universal Multi-Resource Bus, which connects a host to every FPGA on the board for configuration and monitoring. UMRBus enables a sophisticated co-simulation environment and transaction based-verification which can be up to 10,000x faster than simulation. “Designers don’t have to wait until all RTL is available – they can use blocks as they become available. Mixing virtual with physical prototypes is what most people do,” said Vivolo.
Three different versions – HAPS-64 with 4 FPGAs, HAPS-62 with 2, and HAPS-61 with 1 – make the family flexible for different design teams and budgets. It’s an interesting system that takes rapid SoC and ASIC prototyping to the next level, with high confidence in the technology behind the IP.
