Switching up the equation to optimize energy efficiency of SoC designs
It wasn’t long ago when power was a distant third in the power, performance, and area triad of system-on-chip (SoC) design concerns. In the last few years, power has risen quickly as a critical concern driving SoC designs. Performance can be analyzed through virtual platforms, the abstract modeling of hardware prototyping. Area can be easily estimated.
Anyone doubting that power is an ongoing worry of mobile device users should take a good look at a recent J.D. Power survey. Battery life was rated as the number one dissatisfaction factor with this group of smart phone consumers – we’ve all seen this in airports as mobile users hover around power kiosks desperately vying for a spot to charge their devices – yet power modeling and analysis remain the most underdeveloped solutions in the design of SoCs even as Moore’s Law slows down and, to compensate, power-consuming complexity is added to designs to achieve performance goals. Energy efficiency has become critical.
While the semiconductor industry moved beyond Excel spreadsheets for calculating power consumption, it continues to rely on ad hoc tools with little or no automation. Examples run from abstract power models without any path to implementation to late-stage tools targeting gate-level or later when change is difficult and costly. All are prohibitively slow and remarkably ineffective.
We can do so much better to fully optimize the energy efficiency of SoC designs, especially for high-growth markets like automotive, Internet of Things (IoT), mobile, networking, and servers. Both hardware developers and software engineers need an exacting way to understand the details of power consumption in their systems and how to improve the energy efficiency in the design and software.
Peering at a project group’s wish list for a power analysis and modeling tool is instructive and starts with much faster solutions that deliver a greater level of accuracy. The solution must be usable for hardware/software co-design to optimize designs for low-power consumption. Power and thermal management is high on the list as well. Support for dynamic and static power is important, as is taking in register transfer level (RTL) and netlist descriptions of the design.
A complete solution is needed to address a wide array of use cases. These include:
- Reducing the power consumption of the hardware
- Changing the software to optimally manage power
- Power sign-off
- IR drop analysis (power grid validation)
- Security vulnerabilities
Today’s project groups are a mix of hardware developers and software engineers, with an emphasis on software engineers, which means the tool should be built to be used earlier in the design cycle. Shifting left in the design cycle offers them greater opportunity to optimize power and gain better energy efficiency.
Embedded software engineers require a solution that offers the performance to run real software scenarios on the design. Otherwise, they can’t understand how their software interacts with the hardware relating to power consumption. Unfortunately, current power analysis solutions are far too slow to address the software engineer’s needs.
Understanding security vulnerabilities via side channel attacks with security IP is another area that is poorly addressed with existing solutions. Again, performance in power analysis tools is critical to run many long scenarios to uncover the vulnerabilities and fix them.
Following the project group’s wish list should be priority one for design tool companies to switch up the equation and give them the power tools they need. Having a solution that achieves both the speed necessary to run a variety of realistic scenarios combined with providing a high level of accuracy will let project groups uncover power problems quickly and identify where to make the fixes.