ams releases 0.30 µm process for ultra-low noise sensing and analog ICs

ams AG has announced the 0.30 µm High Performance Analog Low Noise CMOS (A30) process, which provides improved noise performance over the company’s 0.35 µm High-Voltage CMOS family through an optical shrink that reduces die size by a factor of 0.9. The A30 process is suited for ultra-low noise sensing applications and analog read-out ICs that require noise-optimized input stages or high signal-to-noise ratio (SNR).

The A30 process is qualified and manufactured in ams’ 200 mm fabrication facility, with all 0.30 µm elements drawn and verified as 0.35µm devices. The optical shrink is done in the mask shop based on completed GDSII data, and results in smaller die sizes and more dies per wafer.

The A30 technology portfolio features isolated 3.3V devices (NMOSI and PMOSI), isolated 3.3V low Vt devices (NMOSIL and PMOSIL), an isolated high-voltage device with thin gate oxide (NMOSI20T), vertical bipolar transistors (VERTN1 and VERTPH), and an isolated 3.3V super low noise transistor (NMOSISLN), which offers flicker noise on the level of 0.46 pA/√Hz (@1kHz, Ids=1µA @Vds=3V, 10x1.2µm²). Passive devices such as capacitors and resistors complete the offering.

“Foundry customers benefit twice when using the A30 process for their complex ICs: Our super low noise transistor with industry-benchmark flicker noise figures boost performance whereas the optical shrink notably reduces die area of noise sensitive applications,” says Markus Wuchse, General Manager for the Full Service Foundry division at ams.

The A30 process is supported by ams’ hitkit industry benchmark process design kit based on version 6.1.6 of Cadence Design System’s Virtuoso Custom IC technology. hitkit version 4.15 for A30 process is available now at, and more information on the process itself can be found at