How to do functional tests on I2C and SPI monitors with JTAG is explored in new eBook from ASSET InterTech
A new eBook from ASSET(r) InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, explains how the structural test methodology based on the IEEE 1149.1 boundary scan standard, known as JTAG, can apply functional tests to I2C and SPI system monitors during prototype board bring-up and later during production.
Richardson, TX (May 8, 2013) – A new eBook from ASSET® InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, explains how the structural test methodology based on the IEEE 1149.1 boundary scan standard, known as JTAG, can apply functional tests to I2C and SPI system monitors during prototype board bring-up and later during production.
Devices such as temperature sensors, electrical sensors and others which communicate over the Inter-Integrated Circuit (I2C) and Serial Peripheral Interface (SPI) buses often keep track of certain conditions or operating parameters in electronic systems. When the condition exceeds a predefined range, the monitoring device will take an action, such as alerting the system’s central processing unit (CPU).
“Most design engineers have relied on functional tests to verify that I2C and SPI monitoring devices were functioning properly. The problem with this is it assumes a functional circuit board, which often isn’t the case when prototypes are being brought up for the first time,” said Kent Zetterberg, product manager for ASSET InterTech. “In addition, functional tests take a lot of time and effort to develop, so many times they’re not available until it is too late for board bring-up. And the diagnostics of functional test leaves a great deal to be desired. It is very difficult for a functional test to isolate the cause of a fault. This is not the case when a functional test based on a structural test method like JTAG is deployed.”
The eBook, titled “Functional Test on I2C and SPI System Monitors with JTAG,” explains how a method based on device models can simplify and accelerate the development of functional tests for I2C and SPI monitors. These same routines can also program monitoring devices with their operating code. JTAG-based functional tests can be deployed early during design when prototypes are being brought up so that both structural and functional defects can be detected in one step. These same routines can migrate with the circuit board design when it transitions into volume manufacturing, eliminating the need to re-develop some of the board’s production tests. This reduces test costs, accelerates a new product’s time-to-market, and improves fault coverage and diagnostics in manufacturing.
“Functional Test on I2C and SPI System Monitors with JTAG” is available now on the ASSET web site at: www.asset-intertech.com/Products/Boundary-Scan-[...] . Other informative eBooks, white papers and videos on JTAG and IJTAG, embedded instrumentation and other topics relating to board and chip debug, validation and test can be downloaded from: www.asset-intertech.com/News/White-Papers
About ASSET InterTech
ASSET InterTech is the leading supplier of tools for embedded instrumentation for design validation, test and debug. The ScanWorks platform provides automation, access and analysis tools in one environment. Users can quickly and easily validate and test semiconductors, circuit boards or entire systems during every phase of a product's life, including design, manufacturing/repair and field maintenance. ASSET InterTech is located at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.
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