SANTA CLARA, Calif., May 22, 2009 – Azuro, Inc. a leading provider of software tools for semiconductor chip design, today announced the first customer tapeout using its Rubix™ clock concurrent optimization tool. This achievement, together with several benchmark successes in the first quarter of 2009, has lead Azuro to promote Rubix status to general availability.

“Rubix delivered compelling performance wins out of the box on multiple engagements in Q1. This benefit is being traded easily for reduced area or leakage, and also gives a dramatic increase in designer productivity,” said Barb Acosta, vice president of sales and business development at Azuro. “With Rubix we are able to expand rapidly into new design groups with different design challenges to those addressed by our PowerCentric clock tree synthesis solution.”

Rubix leverages an identical flow integration interface to PowerCentric™ and includes a full superset of its capabilities. Pricing is available for existing PowerCentric users to upgrade seamlessly to Rubix at any time during their license term.

For more information on the clock concurrent optimization technology behind Rubix, see the “Clock Concurrent Optimization” white paper at www.azuro.com/rubix/white-paper.html.

About Azuro

Azuro is an electronic design automation (EDA) company supplying software tools to design digital semiconductor chips. The company’s unique clock tree synthesis and physical optimization technologies make chips faster, reduce chip power and dramatically accelerate chip time to market. Customers of Azuro’s software include Broadcom, NVIDIA, NXP, ST Microelectronics, and Texas Instruments (www.azuro.com/cust/cust01.htm). Azuro products are included in TSMC’s Reference Flow and Integrated Sign-off Flow. The company was founded in 2002, and has completed over 50 tapeouts since launching its first product in 2005. Azuro is headquartered in Santa Clara, CA with R&D in Cambridge, UK, and is privately held.

Rubix and PowerCentric are trademarks of Azuro, Inc.

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Keywords: clock tree synthesis, physical optimization, timing optimization, clock concurrent optimization, design complexity, ideal clock, propagated clock, useful skew, skew, on-chip variation, low power, semiconductor, integrated circuit, IC, electronic design automation, EDA, RTL, chip design

Contacts:

Azuro – Marc Swinnen, (408) 464-7350, marcs@azuro.com

Cayenne Communication - Linda Marchant, (919) 451-0776, linda.marchant@cayennecom.com