IEEE754-2008 Compliant, GP-GPU-Compute Engine for FPGAs now Open-Source
Multi-threaded, GP-GPU-Compute engine in Verilog RTL (beta) is now available for free download and evaluation.
|Multi-threaded, GP-GPU-Compute Engine with AXI4 I/F|
Austin, TX-- (Beta) Verilog RTL for an open-source, single-precision, GP-GPU-Compute engine is now available for free download and evaluation. Apart from making it as simple as possible, among the many design goals is to make it IEEE754-2008 compliant where possible and within reason in terms of FPGA resource utilization.
A "preliminary" information sheet can be downloaded here:
Dubbed the “SYMPL” GP-GPU and featuring an AMBA-AXI4 slave interface, it is a multi-threaded design and features FloPoCo-generated floating-point operators. While the FloPoCo-generated floating-point operators, standing alone, presently are not fully compliant, the Verilog wrappers that house them in the SYMPL GP-GPU-Compute engine do some things to help remedy that. The single-precision, floating-point operators incorporated into SYMPL include: FADD, FSUB, FMUL, FDIV, SQRT, LOG, EXP, FMA(fused-multiply-add), DOT (sum-of-products), ITOF and FTOI. With exception to DOT, each operator can accept new operand inputs every clock cycle without producing stalls.
Among SYMPL's many IEEE754-2008 features: compliant default, alternate-immediate and alternate-delayed exception handling; generation/delivery of non-signaling NaNs with diagnostic payload for invalid operations; signaling-NaN-responsive (invalid operation); capture registers/mechanism for alternated-delayed exception handling permits delivery of substituted results; gradual underflow (subnormals) without automatic flush-to-zero; and directed rounding specifier built into each instruction, with “nearest” being default rounding mode, but with the ability to specify round-to-zero, positive infinity, or negative infinity for any non-conversion operation.
RTL source code, test-bench and example assembly language/object code can be downloaded here:
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