New eBook shows how to avoid conflict among embedded test access ports when integrating SoC IP blocks
- Cores and other blocks of intellectual property (IP) often feature a test access port (TAP). When multiple such IP blocks are integrated into a system-on-a-chip (SoC), their TAPs become embedded. Such embedded TAPs (eTAP) are prone to conflict with each other, which can prevent engineers from accessing IP blocks during SoC debug, validation or test. A new eBook from ASSET InterTech (www.asset-intertech.com) explains how some up-front planning will avoid these problems.
|Mixing Embedded eTAPs | 1149.1, IJTAG, Software Debug|
Richardson, TX – Cores and other blocks of intellectual property (IP) often feature a test access port (TAP). When multiple such IP blocks are integrated into a system-on-a-chip (SoC), their TAPs become embedded. Such embedded TAPs (eTAP) are prone to conflict with each other, which can prevent engineers from accessing IP blocks during SoC debug, validation or test. A new eBook from ASSET InterTech (www.asset-intertech.com) explains how some up-front planning will avoid these problems.
“Unfortunately, having defined the TAP as the primary and only test access port on a chip, the IEEE 1149.1 JTAG standard doesn’t provide any guidance on the integration of eTAPs into an SoC,” said Adam Ley, one of the three authors of the eBook and ASSET’s chief technologist, non-intrusive board test and JTAG. “Without some forethought during design, accessing all of the eTAPs later with engineering tools could be difficult or even impossible. Useful guidance for integrating multiple eTAPs can be found in the IEEE 1687 IJTAG and IEEE 1149.7 standards, but having this information in two documents makes it more difficult to use. So, we’ve compiled the information engineers need most to get around this problem and remain compliant with all standards in our new eBook.”
Titled “A Modest Proposal for Chip-Level Consolidation of a Multiplicity of Embedded TAPs with Consideration for JTAG Boundary Scan, JTAG Software Debug, and IJTAG Instrumentation Networks,” the new eBook recommends several design best practices, which, if followed, will allow access to an SoC’s IP blocks. The eBook is free and available now on the ASSET web site in the eResources center at www.asset-intertech.com/Footer/eBooks/Mixing-Em[...]
Other informative eBooks, white papers and videos on issues relating to chip, board and system debug, validation and test also can be downloaded from: www.asset-intertech.com/eResources
About ASSET InterTech
ASSET InterTech (www.asset-intertech.com) is a leading supplier of tools to debug, validate and test software and hardware. The company’s SourcePoint™ software debug and trace platform and ScanWorks® platform for embedded instruments work in tandem to give engineers real insight from code to silicon. SourcePoint is a best-in-class, powerful debugger that includes advanced trace tools to gather data from code and quickly debug complex embedded software systems. ScanWorks controls instruments embedded in chips to test and validate chips and circuit boards. Together they empower engineers with tools and technology for the entire life-cycle of a system, beginning with software and hardware development, on to design validation, through software/hardware integration, and eventually testing the product in manufacturing and field service. ASSET InterTech is located at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.
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