New white paper reveals shrinking eye diagrams and signal integrity problems on high-speed buses -- Bandwidth tests often detect degraded performance on DDR, PCI Express, Intel QPI, USB and others high-speed buses
Factors like jitter, inter-symbol interference (ISI), crosstalk and others can create havoc on the signal integrity of high-speed serdes and memory channels, making maximum bus speeds difficult to achieve in practice. Compounding this predicament is the fact that channel speeds keep increasing from one generation bus technology to the next. To avoid potential problems with high-frequency bus traffic the signal integrity on the bus must be validated during each of the major phases of a system's life cycle, including design/development, manufacturing and as an installed system in the field. If the signal integrity on a serdes channel is not what it should be, steps should be taken to correct the problem and improve system performance.
Richardson, TX (Nov. 27, 2012) – A new white paper from ASSET® InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, points out how increasing bus speeds on circuit boards could create havoc for signal integrity on those buses, in turn degrading the bus’ throughput performance. Each new generation of a high-speed bus typically runs at a higher signal frequency, but this decreases the margin for error on the bus, making it more sensitive to disruptions from jitter, inter-symbol interference (ISI), crosstalk and other factors.
To avoid potential problems on high-speed buses like DDR3, PCI Express, Intel® QPI, Serial ATA, USB and others, bus performance must be validated during each phase of a system’s life cycle, including design/development, manufacturing and as an installed system in the field. Unfortunately, effectively and economically validating the signal integrity on a high-speed bus has become more difficult as the limitations of legacy probe-based test equipment such as oscilloscopes have become more obvious in recent years. Now though, non-intrusive software-driven test methods based on embedded instrumentation are providing alternative validation solutions that are more cost-effective and deliver observed signal integrity data.
The white paper, titled “Bandwidth tests reveal shrinking eye diagrams and signal integrity problems”, can be downloaded from ASSET’s web site at www.asset-intertech.com/Products/High-Speed-I-O[...]
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About ASSET InterTech
ASSET InterTech is the leading supplier of tools for embedded instrumentation for design validation, test and debug. The ScanWorks® platform for embedded instruments provides automation, access and analysis tools in one environment. Users can quickly and easily validate and test semiconductors, circuit boards or entire systems during every phase of a product's life, including design, manufacturing/repair and field maintenance. ASSET InterTech is located at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.
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