RISC-V SoC development toolkit released by Codasip, UltraSoC
Semiconductor IP vendors Codasip and UltraSoC have announced plans to integrate Codasip’s Codix-Bk series of RISC-V-compliant processor cores with the UltraSoC debug, analysis, and bring up environment to reduce development time for system on chip (SoC) developers designing with the RSIC-V instruction set architecture (ISA). Rather than adapt legacy SoC development solutions, the RISC-V-optimized implementation platform will combine Codasip’s model-based processor IP and infrastructure with the UltraSoC toolkit in a complete solution that also provides analytics and improvement capabilities.
"RISC-V adoption continues to accelerate with ultimate success requiring the ecosystem evolve beyond initial processor specifications with a focus on the challenges of the SoC creators,” says Rick O’Connor, Executive Director of the RISC-V Foundation. “We're excited to see Codasip and UltraSoC working together to make customers’ RISC-V based designs a reality."
Codasip’s Codix-Berkelium (Bk) series of processor IP includes standard peripherals, and enables development with operating systems ported to the RISC-V architecture, including Linux and FreeRTOS. Codix-Bk cores include support for the RISC-V RV32IM and RV64IM architectures with 32- and 64-bit registers, contain 3-stage or 5-stage pipeline options, and include optional floating-point extensions or atomic instructions, with the latter including pre-fetch, data cache, and interrupt support. Cores are available in 40LP processes (< 0.10mm² in), with smaller sizes achievable on the company’s ZScale architecture.
“Our customers demand more than just traditional processor-based debug in order to meet the needs of the IoT era,” says Karel Masarik, CEO, Codasip. “UltraSoC’s broad range of capabilities combined with our commercially proven processor infrastructure, supported on our RISC-V series of Codix-Bk processors, drastically accelerates SoC deployment. We are excited by what this collaboration enables and the benefits it delivers to the new era of RISC-V based SoCs.”