UltraSoC moves SoC debug into the 21st Century with CoreSight compatibility and more
New features enable universal debug capability with interworking between legacy signal-based architectures and advanced message-based systems
UltraSoC, the leading provider of on-chip monitoring and analytics solutions for complex systems-on-chip (SoCs), today announced significant enhancements to its product, allowing users to integrate legacy signal-based systems with the company’s message-based architecture. The new capabilities are particularly beneficial to SoC designers working with the range of processor cores from ARM and its associated debug system, CoreSight.
UltraSoC’s vendor-independent technology allows engineering teams to understand what is really happening inside the SoC, non-intrusively and at wirespeed. This enables them to control and monitor the behavior of any on-chip structure – be that a processor, third-party block, custom logic or bus – in active operation. Such capabilities are essential for the engineers whose task it is to ensure that the device and its software are functioning correctly. The features announced today provide a bridge between UltraSoC’s infrastructure and traditional signal-based systems such as CoreSight, so UltraSoC provides truly universal debug capabilities with faster, more reliable development and performance profiling.
“UltraSoC is a 21st-century solution to the growing crisis in chip design,” said Rupert Baines, UltraSoC CEO. “Modern SoCs are massively sophisticated, and are just too complex for architects to fully understand or predict using traditional debug techniques. The world has moved away from a signal-based approach to message-based architectures: the success of network-on-chip (NoC) companies such as Sonics, Arteris and NetSpeed is testimony to this. But customers have made substantial investments – both in terms of dollars and in intellectual property – in the older signal-based technologies. We bridge that gap, with a ‘smart’ vendor-neutral approach that helps developers who employ IP from several different suppliers, or who need more than simple CPU monitoring to debug and optimize their designs.”
By interworking smoothly with signal-based products such as CoreSight, UltraSoC enables a holistic and fully-featured solution for on-chip debug and performance analysis, including monitoring of custom logic; transactions on common bus structures such as AXI and OCP; monitoring of processors, including ARM, MIPS and XTensa cores; support for custom logic; deadlock detection; optimization; and generation of meaningful performance metrics such as latency and best/worst/average utilization. The UltraSoc functionality is non-intrusive, operates at system speed and integrates functionality to intelligently filter signals to reduce trace bandwidth and efficiently highlight problems.
Today’s enhancements to the UltraSoC IP portfolio include a new trace receiver module within UltraSoC’s silicon IP offering, which enables data captured within the signal-based system (for instance ARM’s Trace Bus (ATB) for data captured within CoreSight about the operation of an ARM processor) to be transferred to the UltraSoC infrastructure and integrated with corresponding information from the wider system. The complementary trace communicator functionality is also supported, with UltraSoC messages – such as information from other vendors’ IP or from custom logic – sending information into the signal-based sub-system. With standard features such as run control, alongside more sophisticated functions such as cross-triggering, conditional-trace triggering and trace filtering, as well as automated statistics and logic, this provides a much more capable infrastructure than was previously possible.
Engineers can use UltraSoC to replace legacy solutions (whether in-house or CoreSight); or the technology can be deployed as a fully compatible “wrapper” to extend them, integrating them with other parts of the system and enabling a unified, coherent solution across the whole SoC.
UltraSoC will be demonstrating these new capabilities for the first time in public at ARM TechCon (Booth 215, Santa Clara Convention Center, CA, 10 – 12 November 2015) and subsequently at Semisrael Expo (Booth 27, Avenue Convention Center, Airport City, Israel, 17 November 2015).
Booth #215, ARM TechCon, Santa Clara Convention Center, 10 – 12 November 2015
Booth #27, Semisrael Expo, Avenue Convention Center, Airport City, Israel, 17 November 2015