Vennsa Picks Verific Design Automation's de facto Front End Software
SystemVerilog, PSL Analyzer, Static Elaborator Integrated with Automated Debug Tool
Vennsa Technologies Inc., the leader in automated debugging and error localization software, today announced that de facto standard front-end software from Verific Design Automation serves as the front end for OnPoint™, its breakthrough tool in automated debugging.
Vennsa, a Verific customer since its inception, licenses the SystemVerilog and property specification language (PSL) analyzers and elaborators. Both have been tightly integrated with OnPoint, revolutionary software that automates completely the manual root cause analysis performed by engineers today once a functional failure occurs.
OnPoint is a sophisticated tool that picks up where formal verification and simulation tools leave off by automatically pointing to lines of code where a failure can be fixed with no interference by the engineer.
“Verific’s software is robust and dependable, which allows our engineers to focus on our core expertise, automated debugging,” says Dr. Sean Safarpour, Vennsa’s chief technology office and vice president of engineering. “On the business side, Verific has been an extremely supportive business partner from our university spin-off days to today.”
Verific’s software serves as the front end to a variety of Electronic Design Automation (EDA) and Field Programmable Gate Array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. The software is written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and comes with support and maintenance.
“Vennsa grew out of research at the University of Toronto and I’m proud to report that the team has been using our software from day one,” remarks Michiel Ligthart, Verific’s chief operating officer. “It’s been a great experience being part of the process and watching Vennsa grow as it develops a revolutionary CAD tool for a real-life verification pain.”
Vennsa Technologies Inc. is dedicated to debugging and error localization. Its breakthrough OnPoint™ tool is the industry’s only automated debugging software that localizes the source of functional errors without any user guidance. When failures occur, OnPoint helps engineers quickly identify the root cause of errors and remove the bugs. Vennsa is located in Toronto, Ontario, Canada. Telephone: (416) 829-0091. Email: email@example.com. Website: www.vennsa.com.
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, is a leading provider of SystemVerilog, Verilog and VHDL front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: firstname.lastname@example.org. Website: www.verific.com.