XJTAG Delivers Fast ISP Flash Configuration for ARM-Based FPGA SoCs

XJTAG Delivers Fast ISP Flash Configuration for ARM-Based FPGA SoCs
XJTAG Delivers Fast ISP Flash Configuration for ARM-Based FPGA SoCs

• XJFlash now supports In-System of Xilinx Zynq, Altera Cyclone V SoC and other Dual ARM Cortex-A9 based FPGA SoCs

• Experience up to 20 times faster Flash programming cycles through a single JTAG port

• Delivers programming times better than or comparable to Ethernet/SD Card based solutions without the need for any additional hardware

• Significantly increases throughput at the production stage

• Can be fully integrated with 3rd Party Executives

CAMBRIDGE, England, 4 Oct 2016 — XJTAG®, a world leading supplier of boundary scan technology, announces extended capability to its high-speed In-System Programming (ISP) technology, XJFlash. For the first time, this brings the benefits of XJFlash to devices connected to the processor sub-system of dual ARM-Cortex-A9 based FPGAs.

Using XJFlash, new and existing customers will experience programming times as much as 20 times faster than existing solutions when configuring memory attached to the processor sub-systems of the industry’s leading FPGA SoCs, such as Xilinx Zynq and Altera Cyclone V SoCs, which feature dual ARM Cortex-A9 processors.

The use of FPGAs with integrated processor sub-systems is increasing. While these sub-systems are fully integrated into the FPGA fabric, they feature their own, dedicated, external non-volatile program memory, connected to the physical pins of the FPGA. Configuring these memories in both development and production environments is normally a slow and often complex process. With XJFlash these memories can now be configured simply and at high speed through the JTAG port of the FPGA, without the need for any additional PCB connections.

With this latest development, XJFlash is now able to access and configure memory devices connected to a wider range of FPGAs. This will significantly decrease the time taken to configure on-board memory during development, production and rework. Support for the ARM Cortex-A9 based SoCs extends to partial reconfiguration and optimised erase, delivering further productivity benefits. This enables memory devices to be partially erased and reconfigured without having to reprogram the entire device and also minimises the erase time when regions of a device are already blank.

XJFlash forms part of XJTAG’s portfolio of powerful JTAG tools. As well as needing no additional programming hardware, XJFlash is proven to deliver significantly faster configuration cycles than other programming technologies, for all types of non-volatile memory, including SPI, QSPI and parallel NOR Flash.

Offering Maximum Flexibility

XJFlash can be used wherever XJTAG can - as part of a standalone XJTAG test system , or fully integrated into 3rd Party Test Executives (such as LabVIEW) in systems which also use other Equipment (ATE).

Existing licensees will automatically benefit from the expanded capabilities of XJFlash. New customers can contact XJTAG or one of its distribution partners for a demonstration. Initial support for FPGA/Processor platforms includes Xilinx Zynq-7000 SoCs, and Altera Cyclone V SoC devices. Both families feature a dual ARM Cortex-A9 processor sub-system.

To learn more about XJFlash, visit www.xjtag.com/xjflash

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