• Features Altera EPM7256S CPLD with 256 macrocells, up to 5,000 usable gates, and 15-nsec propagation delay
• Enables digital I/O, timers, UARTs, PWM, shift registers, state machines, and many other I/O devices to be developed and downloaded from a desktop computer to the CPLD
• Can be powered separately and run as a stand-alone board
• In-system programming through the JTAG port
• Altera's MAX+PLUS II software allows CPLDs to be designed by using schematic capture or high-level description languages
• The CPLD connects to all of the signals on the PC/104 bus, four LEDs, four plug-on jumpers, a 32-pin JEDEC socket, a 40-pin connector, and a 34-pin connector
• Small breadboard area for custom circuitry

See also:

• Micro/sys, Inc. products
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