Mercury Systems

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Four A/D converters (14-bit at 105 MHz sampling rate); each followed by an Altera Stratix FPGA with custom IP to implement a wide band receiver and FFT engine


  • Two large user-programmable Xilinx Virtex-II Pro FPGAs each with a total of 512 MByte DDR SDRAM.?These FPGAs connect directly to each other through four LVDS data?links that each provide 622 MBytes/second throughput
  • ?The FPGA resources are also?available to implement custom processing functions (beamforming, direction-finding, etc.) according to user specifications
  • One control/output FPGA with associated 256 MByte DDR SDRAM which outputs data to the appropriate data bus, dual RACE++, serial Rapid I/O, or other Vita 41-defined protocol
  • The PPC 405 processor in the FPGA implements high-level "meta commands" to process data framing, tuner frequency, decimation rates, and FIR filter coefficients
  • One 16-bit at > 2 GBytes/second full duplex parallel Rapid I/O Interface on the board's front-panel, the four analog inputs, a clock input, a sync input, and a sync output; the latter of which is useful for supplying a sync signal to a second ECDR-4-1405 to maintain data coherency across the boards.

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