Calypso-V6
TEK Microsystems, Inc. — November 2011
The new Calypso-V6 supports either two 12-bit analog-to-digital converter (ADC) channels at 3.6 GSPS (Gigasamples per second) or six channels at 1.8 GSPS.Like all members of the QuiXilica-V6 VME / VXS family, the Calypso-V6 is compatible with legacy VME systems as well as newer ANSI/VITA 41 VXS based systems and combines the highest density FPGA processing available in any 6U form factor with the ultimate in ultra wide band ADC signal acquisition.
- Two 12-bit ADCs at 3.6 GSPS, Also supports 6 channels @ 1.8 GSPS
- Three Xilinx Virtex®-6 FPGAs
- Sample-accurate trigger input
- Five GB DDR3 SDRAM memory
- Two fully independent banks (72 Mb/bank) of QDRII+ memory on backend FPGA
- Single front panel clock input
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