• 1 socket built in with the ability to use a transition module to add a second socket. Socket operates in true IDE mode
• 8 and 32 MHz operation IP Module bus operation
• ID PROM is byte wide, internal control register is word wide, CompactFlash module is word wide for data path and byte wide for control
• The IDPROM is build into the Xilinx
• "PROM" contents are available to determine the current revision of the IP-CF and to determine the slot location
• The user manual has the expected data content definition
• Wwrite cycle to the CompactFlash is pipelined with an early termination to the IP host
• Pipelining reduces the access time in writing to the Flash memory
• Read cycles wait for data to be available from the memory module
• Control registers are read-writeable I/O, ID, INT spaces supported
• Interrupt level 0 is used to route the CompactFlash interrupt to the host computer
• Interrupt is maskable and pollable
• +5 V internally, +5 V routed to CompactFlash socket
• P5V also routed to IO connector via "self-healing" fuse
• Current levels determined by hardware installe
• An oscillator position is provided on the fab
• The oscillator is not used with the base design
• Custom versions with special frequency requirements can be supported

See also:

• IP Compact Flash Datasheet
• Dynamic Engineering products
• Restart Search

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