J-SCAN Version 2.1, the newest release of its high-speed, low-cost boundary-scan debug and programming tool.
- This new technology allows circuit designers to facilitate early test development, thereby shortening the development cycle and prototyping process.
- Version 2.1 of J-SCAN communicates to the target with a USB 2.0- and USB 1.1-compatible interface that runs in high speed or full speed modes.
- This gives a performance increase of more than 10X compared to the previous version of J-SCAN. Additionally, J-SCAN 2.1 has full support for serial peripheral interface (SPI) Flash programming, supporting those systems using field-programmable gate arrays (FPGAs) and other embedded devices.
- J-SCAN provides significant advantages compared to logic analyzers and oscilloscope probes, permitting designers to observe the behavior of the pins under a ball grid array (BGA) device in real time on their PCs.
- The J-SCAN debug and programming tool also allows designers to manually place the pins to any logic state with a simple point-and-click of the mouse.
- Engineers can observe logic state transitions and instruction addresses sent and received across individual pins, providing an unprecedented level of visibility in debugging SOCs, integrated components and new board designs.
- For the first time, the IC designer now has visibility into and control of every pin.
- The included USB 2.0 download cable enables programming times of minutes, rather than hours or days.
- Utilities to program FPGAs and complex programmable logic devices (CPLDs) are also available.
- J-SCAN works independently of any logic inside the JTAG device, so no special firmware, code or logic needs to be installed.