• Automated RTL implementation
• Automatically generates RTL and a verification test bench from a Simulink system-level specification
• No hand-coding of any RTL is required
• Provides a set of functional blocks commonly used in DSP design including filtering (FIR, IIR), transforms, math functions, CORDIC, signal operations, memories, and control logic
• These functions are technology-independent and tightly integrated into The MathWorks environment, allowing the algorithm designer to utilize Simulink features such as discrete-time simulation, multi-rate management, fixed point quantization, scope debugging, and more
• FPGA hardware independence: allows algorithm behavior to be captured in Simulink without preselecting the specific FPGA device for implementation
• Automatically implements an optimized architecture in RTL based upon timing and area requirements
• Multi-channel system from single-channel specification: Enables quick what-if analysis on channel capacity by automatically generating a pipelined system from a single channel specification
• Area-speed tradeoffs - Math intensive DSP algorithms easily consume large numbers of expensive hardware functions such as multipliers
• Analyzes the design to automatically find opportunities for sharing these resources, saving design iterations and significant area

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