• By extracting behavior such as Finite State Machines, multipliers, and memories from RTL code and starting synthesis at this level, the Synplify Pro product optimizes a design globally for improved performance and at the same time can run faster and handle larger designs
• By selecting a switch, a designer can tell the tool to automatically move registers inside combinatorial logic in order to balance timing delay and improve circuit performance by as much as 20 percent
• Retiming may be used on a global level or selectively
• The HDL Analyst RTL graphical analysis and debugging tool provides instant graphical views of both high-level block diagrams and gate-level schematics linking back to the RTL source code, making debug and code optimization fast and easy
• Critical paths are quickly highlighted and linked back to RTL source
• The FSM Explorer automatically finds state machines in the design, then evaluates alternative encoding styles and selects the one giving the best solution for the specified timing constraints
• FSMs are displayed as bubble diagrams, providing an easy-to-read graphical representation of results
• Offers a formal verification mode where optimizations are recorded and passed on to tools such as Cadence's Conformal product for this purpose
• Interfaces to popular HDL simulators and is tightly integrated with place and route tools from Actel, Altera, Lattice, QuickLogic, and Xilinx

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• Synplicity products
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