Synplify Premier

Synopsys, Inc.

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Graph-based Physical Synthesis; fast timing closure and a push-button performance boost of up to 20 percent

FEATURES

  • RTL-based Verification Technology; offers the fastest method of finding functional errors in a design thanks to simulator-like visibility into a live, running FPGA with real-world stimulus
  • Automatic Handling of DSP functions; infers DSP functions from RTL and maps into vendor's DSP hardware (such as MAC)
  • ASIC design-style support; built-in gated clock conversion and a DesignWare compatible library enables ASIC code to be implemented into an FPGA without modification
  • Fast compile times; synthesizes even the largest design in a fraction of the time of other tools

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