• These highly integrated network flow processor engines are designed to team with Intel architecture processors using the Single Root I/O Virtualization (SR-IOV) features of PCI Express Gen 2 to provide 256 queues for I/O coprocessing
• The 40 microengines are integrated into an optimized high-speed interconnect, with programming tools available to help designers utilize the architecture
• To integrate with high-speed networks, NFP-32xx incorporates 25 Gbps Interlaken, SPI 4.2, and 10 Gbps XAUI interfaces
• On-chip security processing is also important, with crypto engines supporting RC4, Triple Data Encryption Standard (3DES), Advanced Encryption Standard (AES), Secure Hash Algorithm 1 (SHA-1), and SHA-2
• The result, according to Netronome, is the ability to perform 20 Gbps of Layer 2-7 deep packet processing with line-rate security features, all in an optimized power profile

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