• At its core is the C Data Flow (CDF) modeling paradigm, which enables the most efficient description of digital signal processing systems which may be implemented in dedicated digital hardware or embedded software
• SPW Hardware Design System (HDS) is a key component in the SPW product family
• It accelerates the hardware design, verification, and analysis of complex, algorithm intensive Digital Signal Processing (DSP) systems
• SPW HDS flow provides graphical RTL design capabilities with parameterized design capture using the SPWC Data Flow (CDF) modeling that enable reuse
• It also includes a large library of complex system building blocks that contributes to substantial reductions in product development time
• HDL simulators are integrated through direct co-execution where the CDF simulation is a part of the HDL design, hence making communication overhead go away
• This is critical as testbenches developed with SPW have very high value if they can be effectively used to verify generated RTL that may contain handwritten RTL as well
• SPW Hardware Design System (HDS) Proven solution with high quality of results
• Correct by construction RTL design
• Rapid, divide and conquer RTL verification
• Rapid system performance optimization of detailed hardware design

See also:

• Synopsys, Inc. products
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