• Designed around a Virtex-6 FPGA front end processor (FEP) card
• Combining data and control plane topology, the architecture supports multi-processor capability via two clusters for front-end and back-end processing
• The OpenVPXTM standard backplane profile has two separate star sections that are established through a data and control plane switch, handling both PCIe and GigE links
• All slots in the backplane include control plane interconnects
• The front end FPGA cluster performs incoming digital signal processing in advance of higher level back end operations

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• Elma Electronic Systems products
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