Platform Architect
Synopsys, Inc. — July 2011
Broadest commercially available portfolio of pre-instrumented SystemC TLM IP models for architecture exploration and validation, including: traffi c generators, interconnect models, memory controller models, and processor models
- Application task analysis for early optimization of multicore systems
- Model debugging using TLM port transaction tracing and analysis
- Sensitivity analysis using pivot charts to aggregate and explore results
- Extensive set of performance analysis views to measure latency, throughput, utilization, and efficiency
- Ability to combine hardware and software analysis for performance validation
- IEEE 1666 SystemC TLM standards-based environment
- CoStart methodology guidelines and examples as well as CoStart Enablement Services
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