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Embedded Computing Design

PCI 9656

PLX Technology — October 2000

PCI 9656

A 64-bit, 66 MHz PCI I/O accelerator

  • General-purpose bus mastering device available for Motorola MPC850/860 PowerQUICC and generic 32-bit, 66 MHz local bus based designs
  • Incorporates PLX's Data Pipe Architecture technology, featuring DMA engines, programmable Direct Master and Direct Slave data transfer modes, and PCI messaging functions
  • CompactPCI Hot Swap compliant
  • D3COLD Power Management Event (PME) Generation meets the latest requirements for PCI Power Management silicon, enabling adapters that meet the PC 2001 System Design Guide requirements for Microsoft Windows logo certification
  • Embedded Host Control Signal Configuration, PCI Arbiter, and PCI Type 0 and 1 Configuration Cycles
  • DMA Descriptor Ring Management enables complete hardware management of DMA descriptors
  • Supported with a complete reference design kit (RDK) with software debug support, and a hardware development kit (HDK) CD-ROM

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