Implementing High Performance EMBEDDED Computing Hardware

The high performance solutions discussed in this whitepaper comprise a system host board (SHB), backplane in a system designed exclusively to solve the data throughput needs of high density embedded computing applications. High-end embedded applications require robust computing performance, so the SHB and system-level technologies must be able to take full advantage of the ever increasing number of processor cores and the corresponding increase in native 3.0 links available on the processor die.

Several hardware solution platforms are discussed including a dual-processor system host board and related PCIe Gen3 referred to as HDEC. High Density Embedded Computing; or HDEC, is a new SHB and backplane standard that builds upon the basic goodness of the ® 1.3 spec. by increasing the base number of PCIe lanes between the HDEC Series SHB and backplane from 20 lanes to a maximum allowable limit of 88 lanes. Today’s Intel® Xeon® E5-2600 v3/v4 processor options supported on the HEP8225 HDEC Series system host board delivers 80 lanes of PCI Express down to a backplane for an impressive increase of 300% of over a PICMG 1.3 SHB. Future Intel® Xeon® processor options will enable 88-lane PCIe link expansion capability that was built into the HDEC Series base specification.

New data storage strategies utilizing PCI Express-driven, M.2 form factor, NVMe storage modules are discussed including read/write data performance and throughput speed comparisons with other storage devices such as SSDs and HDDs. The whitepaper also discusses several single-processor high performance embedded hardware solutions including a modular 1U system design approach that supports commercial-off-the-shelf (COTS), full-length PCI Express plug-in cards in a real-word application.