Several hardware solution platforms are discussed including a dual-processor system host board and related PCIe Gen3 backplanes referred to as HDEC. High Density Embedded Computing; or HDEC, is a new SHB and backplane standard that builds upon the basic goodness of the PICMG® 1.3 spec. by increasing the base number of PCIe lanes between the HDEC Series SHB and backplane from 20 lanes to a maximum allowable limit of 88 lanes. Today’s Intel® Xeon® E5-2600 v3/v4 processor options supported on the HEP8225 HDEC Series system host board delivers 80 lanes of PCI Express down to a backplane for an impressive increase of 300% of over a PICMG 1.3 SHB. Future Intel® Xeon® processor options will enable 88-lane PCIe link expansion capability that was built into the HDEC Series base specification.
New data storage strategies utilizing PCI Express-driven, M.2 form factor, NVMe storage modules are discussed including read/write data performance and throughput speed comparisons with other storage devices such as SSDs and HDDs. The whitepaper also discusses several single-processor high performance embedded hardware solutions including a modular 1U system design approach that supports commercial-off-the-shelf (COTS), full-length PCI Express plug-in cards in a real-word data center application.