Embedded Computing Design

Subscribe

Receive our complimentary magazine via U.S. Mail or E-mail.

Embedded Computing Design

Accelerating Analog IC Design using High Performance Device Generation

John Zuk, Tanner EDA — September 1, 2010

New approach to accelerating analog layout surpasses full custom and traditional automation methodologies

Full Text: Download PDF

1Despite many efforts to automate design and layout, these tasks remain primarily a full custom process, with the result that analog is occupying a larger and larger portion of the total design cycle time. Efforts to automate analog design have not been successful in the marketplace because the tools have not been able to equal the quality levels of full custom design, are complex to set up and use, and are expensive.

Tanner ’s new tool forgoes full automation in favor of accelerating the layout process by generating key analog design primitives, such as current mirrors and differential pairs. Layout engineers maintain complete freedom to manually place and route these structures as well as being able to tune the output to their specific requirements. Surpassing traditional automation methodologies, this new layout approach dramatically improves layout productivity and reduces design cycle times while generating structures at a level of quality that consistently matches that of the most experienced layout engineers

Topics covered in this article

Leave a Comment