In the last few years, the industry has converged on UVM (Universal Verification Methodology) as the standard verification methodology, which enables both horizontal (design to design) and vertical (block to subsystem to full chip) reuse. With the entire semiconductor industry getting behind one universal methodology, verification IP developers must also ship UVM compatible components. The rapid adoption of UVM is a testimony of the significant needs it is able to address.
By following the principles presented in this white paper, users will be able to write block-level UVM environments that can be reused directly in emulation. This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain over pure simulation and significantly reducing testbench development time for emulation. With this new approach, users command a complete solution that can be used for block, subsystem, and system level verification.