From Simulation to Emulation - A Fully Reusable UVM Framework

According to the 2012 functional study done by the , more than half of total and development time is spent in verification, justifiably so. Design bugs, if not isolated and fixed at an early stage, get very tricky and exponentially costlier to resolve later. It is therefore critical to ensure that the verification process is complete; in that it has covered as many scenarios as possible before tape out. This contrasts with the technological advances in the wider semiconductor ecosystem, which are shrinking the time available to bring out a chip in the market

In the last few years, the industry has converged on (Universal Verification Methodology) as the standard verification methodology, which enables both horizontal (design to design) and vertical (block to subsystem to full chip) reuse. With the entire semiconductor industry getting behind one universal methodology, verification IP developers must also ship UVM compatible components. The rapid adoption of UVM is a testimony of the significant needs it is able to address.

By following the principles presented in this white paper, users will be able to write block-level UVM environments that can be reused directly in . This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain over pure and significantly reducing time for emulation. With this new approach, users command a complete solution that can be used for block, subsystem, and system level verification.

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