PC/104 maintains its presence in embedded systems

The modular PC/104 architecture maintains its relevance in a competitive field.

PC/104 is into its third decade, standing the test of time whilst myriad form factors of yesteryear have faded into irrelevance. So why is PC/104 so persistent? How has it survived? The simple answer for me is the tireless work of the consortium that lies behind its continued success. A collaboration of companies with a common vision, it was formed in 1992 with 12 members, but now has almost triple that. The consortium ensures PC/104’s continued relevance. The spine of a PC/104 stack is the desktop-derived peripheral bus, arguably the key evolution since 1992.

The ’s continued role is to revise and evolve the form factor to encompass that next generation of peripheral bus, from a (now relatively) low 4.77-MHz ISA bus to the blistering 8 GHz that’s available today. The consortium recognizes the importance of backwards compatibility and longevity. Hence, new revisions of the spec optionally retain the previous generation of peripheral bus to satisfy innumerable legacy PC/104 applications.

The form factor’s unique selling point is of course its stackability, a trait that it has exclusively retained while the remaining vast infrastructure of embedded and desktop computing solutions continue to rely on a traditional backplane format. The benefit of stacking is functional scalability, the ability to expand or contract functionality; to facilitate in-situ upgrades of legacy installations or offer a range of configurations effortlessly from a single base product.

The evolution of PC/104 is analogous to that of the ubiquitous Ford Mustang. The old adage “if it ain’t broke, don’t fix it” blissfully applies to both in the retention of their original unadulterated purity; it’s under the hood where technology has kept both at the forefront of their respective industries—PC104’s new engine is PCI express.

PCIe integration into PC/104

The /104 and PCI/104-Express specifications were formally adopted by PC/104 consortium voting members in 2008; the former exclusively providing the PCIe peripheral bus, the latter also retaining the previous generation PCI bus for its famed legacy support. Revisions to larger footprint consortium form factors meant EPIC-Express and EBX-Express, while not supporting stack-through, are valid baseboards to suitably support a rising PCIe/104 peripheral stack.

PCIe/104 satisfies the breadth of I/O diversity required without falling into the incompatibility trap that System-On-Module form factors invariably suffers due to multiplexed pin assignments. PCIe/104 offers two distinct types or fixed I/O configurations that offer flexibility without sacrificing PC/104’s famed scalable compatibility. Type 1 offers a high-speed single by-16 or dual by-8 PCIe link, providing an 8-Gbit/s peripheral bus bandwidth for the latest intensive (invariably video) processing applications. Where such bandwidth isn’t needed, Type 2 trades this for dual 3.0, SATA, by-4 PCIe links, and a low-pin-count (LPC) bus.

Such a diverse range of possible stack configurations are underpinned by the bus’s mechanical flexibility and built-in electronic dynamic compatibility. The flexibility and expandability of the bus and its mechanical layout allow different stack configurations to support an array of diverse project requirements. Intelligent Link Shifting automatically assigns PCIe links throughout the stack and a PCIe/104 to PCI bridge peripheral board adds legacy PCI support where the choice of CPU module can’t.

The PCIe advantage

Due to the computing industry’s obsession with backplane motherboard and slot daughter board methodology, PC/104 finds itself as the only non-backplane system supporting a PCIe peripheral bus. This translates to PC/104 being the only format that lets designers evolve existing solutions to include functionality not envisioned, or technology that didn’t even exist, during the initial design phase.

The evolution of USB to version USB 3.0 has provided unprecedented bandwidth to hot-swappable peripheral devices evolving in parallel with the fixed PCIe bus to which it is effectively a subset. The ubiquitous take up of both has driven down cost so today, their respective capabilities and pricing structure are so similar that they invariably go hand-in-hand, complimenting each other to satisfy either fixed or removable peripheral devices. Such is the design of PCIe, a single high-speed by-16 bus that can be split to provide double the lanes at half the bandwidth, and so on.

The first beneficiaries of a new higher bandwidth peripheral bus are invariably graphics cards, always the first to push the bus bandwidth boundaries and arguably the key driver in the commercial computing arena when next generations get developed. In the embedded space, with ever increasing die density and exponential improvements in integrated graphics chipsets, increasingly the traditional peripheral boards find themselves locally satisfied within a System-On-Chip (SoC). This negates the need for such peripheral bus bandwidth. Additionally, embedded computing technology naturally strives for miniaturization.

The real-estate pressure of often redundant large peripheral bus connectors, in a design that doesn’t fully utilize them, poses a miniaturization bottle-neck. One solution to this problem is OneBank, which is shown in this presentation.

The PCIe/104 and PCI/104-Express specification defines 3 identical and adjacent connectors, integrated into one three-way connector. OneBank replaces that bank of three, superfluous in the majority of small form factor applications, with one connector, identical to the first bank of both Type 1 and Type 2 PCIe/104 connectors. Maintaining the location of the first bank ensures compatibility with existing PCIe/104 boards as well as one another. Offering a 60% reduction in connector size, OneBank increases available PCB real-estate and drives down cost. Support is also retained for lane shifting, the jumper-less auto-configuration of peripheral boards.

Application stories

PC/104 has long been favored in vehicle crash test applications, due to the innumerable variables across differing vehicles and test scenarios that demand complete I/O flexibility. The availability of PCIe in the PC/104 stack offers unprecedented bandwidth to enable more (and faster) measurements than ever before, whether it’s sensors measuring acceleration or strain gauges monitoring metal deformation. PCIe enables multiple high-definition video sources, with unparalleled resolution and frame rates to be captured, and even processed locally within the stack.

With the revolution in personal drones, it’s easy to forget their elder cousins, the . While PC/104 is unlikely to be mechanically viable for a vehicle the size of your palm, it’s long been the staple of traditional UAV avionics, where configurability and reliability is critical. Like the vehicle crash test example, increased peripheral bus bandwidth enables an exponential rise in the capability of integrated sensors and cameras that guide the UAVs while offering greater visibility.

Another member of UAV clan is the , as well as the robots that employ lots of sensors that are typical controlled by and can move the data, using PC/104 Express, to a host CPU for processing. The VineRobot is an example of this technology. The final results are either uploaded to or stored locally on rugged storage devices.

What’s next for PC/104?

With the bandwidth boundaries of PCIe continuing to be pushed as hard as when it first landed, it’s unlikely any entirely new peripheral bus will replace PCIe any time soon. The third generation of PCIe, currently implemented in PC/104, offers a bandwidth of 8 Gbits/s, which is overkill for everything but the latest high-performance applications. The fourth generation will double this to 16 Gbits/s, though the development of interconnects is even further ahead, ready to support 28 Gbits/s.