Chris Eddington, Synopsys, Inc.
High-Level Synthesis (HLS) tools have become increasingly popular for creating ASIC and FPGA hardware with less effort and risk. The productivity gains can be very high, especially when starting from higher abstraction levels like that of Synphony Model Compiler, which uses the Simulink(r) environment and a high-level IP model library for design capture. However, when it comes to integrating an HLS design into a surrounding system or system-on-chip (SoC), the manual effort of interface integration, re-verification and the subsequent risks of errors, debugging and project delay can significantly diminish the HLS productivity gains.
An increasing number of ASIC and FPGA designs are accelerating algorithms and applications directly in hardware (HW) circuits. These HW accelerator cores have become commonplace and are now a key part of product differentiation and the ability to meet market expectations in performance, cost and reliability.