Synopsys processor core puts pedal to the metal for automotive safety

Before getting to the age of driverless vehicles, we had better make sure that cars are safe drivers. To help us along the autonomous highway, Synopsys released the DesignWare ARC EM Safety Enhancement Package (SEP) processor core designed for ISO 26262 embedded automotive and IEC 61508 safety systems. In addition to integrated hardware features that enable Automotive Safety Integrity Level D (ASIL D) compliance, the DesignWare ARC EM SEP core contains a MetaWare Compiler to aid in ISO 26262 code development, making it well suited for Systems-on-Chip (SoCs) targeting applications like motion sensing and advanced driver assistance.

Intended for 65 nm processes, the DesignWare ARC EM SEP core delivers 300 MHz performance with a power consumption as low as 16 mW/MHz, and integrates ECC for single-bit error correction and double-bit error detection. The core is configurable for 32- or 64-bit transactions over ARM, AHB, AHB-Lite, and BVCI interfaces, and includes support for Synopsys Virtualizer, which allows for integration with tools like Mathworks’ Simulink and CANoe from Vector Software, among others.